Test access port (TAP) controllers are known in the art. TAP controllers are used to effect communication of test data on and off chip via what is known as a JTAG (joint test action group) port. The functions of known TAP controllers are defined by IEEE Standard 1149.1-1990 which is hereby incorporated by reference. That Standard defines test logic which can be included in an integrated circuit to provide standardised approaches to testing the interconnections between integrated circuits, testing the integrated circuit itself, and observing or modifying circuit activities during the integrated circuit's “normal” or “user mode” operation.
According to the IEEE Standard, the TAP controller is capable of implementing a variety of different test modes. In each of these test modes, test data is supplied to the integrated circuit via an input pin of the TAP controller, and resultant data following the test is supplied off-chip via an output pin of the TAP controller.
Test data can also be input and output on multiple pins of the chip, not passing through the TAP controller, according to the test mode selected. The resultant data is dependent on the test data and is compared with expected data to check the validity of the test. The input and output pins are referred to respectively as TDI (test data input) and TDO (test data output). Many existing integrated circuits already incorporate a TAP controller of this type with the input and output pins TDI and TDO.
The IEEE Standard also defines a test clock signal TCK and a test mode select signal TMS that are inputs to the TAP controller. Optionally, for use in resetting the device, a test reset input signal notTRST (denoted as TRST* in some scripts) is also defined.
Our earlier patent application EP-A-0840217, which is hereby incorporated by reference, describes a system which makes use of these pins and the TAP controller to increase the communication facilities of the integrated circuit without multiplexing the pins and thereby violating the standard.
In the past, processors (CPUs) were manufactured so that a single processor is incorporated in an integrated circuit, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, the integrated circuit had a plurality of access pins so that information about the CPU, in particular memory addressing information, was externally available from these access pins.
In addition to memory addressing information, it is useful to be able to obtain status information about the internal state of the processor to ascertain for example such events as interrupts, changes in streams of instructions, setting of flags in various status registers of the CPU, etc.
Nowadays, chips are more complex and contain not only a processor on-chip but also its associated memory and other ancillary circuitry. Often there is more than one processor on a chip and those processors may interact. Thus, it is no longer a simple matter to monitor the operation of the processor because the signals which are normally available off-chip no longer provide a direct indication as to the internal operation of the CPU(s).
With the increasing complexity of software designed to run on integrated circuit CPUs it is increasingly important to adequately test the software. This requires techniques for monitoring the operation of the CPU while it executes the software. It is a particularly onerous requirement that the software be monitored non-intrusively while it is operating in real time. There is a requirement for a system to achieve this when there are a plurality of CPUs on-chip that are required to be tested. Even where it is not practical or not possible to achieve non-intrusive monitoring, there is still a requirement to gain access to the operation of software being executed on a plurality of CPUs on-chip with the minimum of intrusion.
One possible method of testing a plurality of CPUs on-chip would be to have individual TAP controllers for each CPU, and a set of external pins for communications off-chip for each of the TAP controllers. However, this is undesirable due to the increased number of pins required, which may not be practical if the limit of available pins has already been reached.
Our earlier patent application EP0982595, which is hereby incorporated by reference, describes an alternative method of testing multiple CPUs on a chip. One TAP controller on-chip interfaces between the external pins and a data adaptor. The data adaptor controls communications to two CPUs for testing. Whilst this system is useful in testing a number of CPUs independently, this system is not particularly flexible.
The inventor has recognised that one problem with the known proposal for testing an integrated circuit with more than one processor is the requirement for each processor to have an appropriate interface to the data adaptor. Such a solution is not available where the plurality of CPUs on-chip are not from the same family or company. Typically a CPU for embedded applications will include a JTAG interface but will have no provision for an alternate interface.
Of concern is the time margins and data rates. It is desirable to decrease the timing margins and/or increase the data rates without adding significantly to the complexity, bandwidth and/or critical timing paths.